[mvapich-discuss] RE: Po

[Greg Lindahl]

On Tue, Feb 21, 2006 at 03:36:17PM -0500, Choudhury, Durga wrote:

> MIPS, however, is a RISC architecture
> and dealing with memory directly (except for loads and stores) are not
> allowed,

No, no, every CPU has atomic ops or equivalent. On MIPS you want to 
use LL/ST, here is the example from the MIPS R4000 Microprocessor
User's Guide, page A-94 (Load Linked instruction):

L1:
	LL	T1, (T0)
	ADD	T2, T1, 1
	SC	T2, (T0)
	BEQ	T2, 0, L1
	NOP

This atomically increments the word addressed by T0. To get
an atomic bit set, change the ADD to an OR.

-- greg