diff --git a/src/mpid/ch3/channels/common/include/mv2_arch_hca_detect.h b/src/mpid/ch3/channels/common/include/mv2_arch_hca_detect.h
index 276114f..829e38f 100644
--- a/src/mpid/ch3/channels/common/include/mv2_arch_hca_detect.h
+++ b/src/mpid/ch3/channels/common/include/mv2_arch_hca_detect.h
@@ -98,6 +98,11 @@ typedef enum {
         MV2_HCA_BROADCOM_BNXTRE,
         MV2_HCA_BROADCOM_END,
 
+/* Yunsilicon Cards */
+        MV2_HCA_YUNSILICON_START,
+        MV2_HCA_YUNSILICON_XSCALE,
+        MV2_HCA_YUNSILICON_END,
+
         MV2_HCA_LIST_END,
 } mv2_hca_types_list;
 
@@ -107,6 +112,7 @@ typedef enum {
     MV2_NETWORK_CLASS_IWARP,
     MV2_NETWORK_CLASS_MARVEL,
     MV2_NETWORK_CLASS_BROADCOM,
+    MV2_NETWORK_CLASS_YUNSILICON,
     MV2_NETWORK_LAST_ENTRY,
 } mv2_iba_network_classes;
 
@@ -115,7 +121,8 @@ typedef enum {
       ((MV2_IS_IWARP_CARD(_x))?MV2_NETWORK_CLASS_IWARP:         \
        ((MV2_IS_MARVEL_CARD(_x))?MV2_NETWORK_CLASS_MARVEL:      \
         ((MV2_IS_BROADCOM_CARD(_x))?MV2_NETWORK_CLASS_BROADCOM: \
-                                    MV2_NETWORK_CLASS_UNKNOWN))))
+         ((MV2_IS_YUNSILICON_CARD(_x))?MV2_NETWORK_CLASS_YUNSILICON: \
+                                    MV2_NETWORK_CLASS_UNKNOWN)))))
 /* Check if given card is IB card or not */
 #define MV2_IS_IB_CARD(_x) \
     ((_x) > MV2_HCA_IB_TYPE_START && (_x) < MV2_HCA_IB_TYPE_END)
@@ -144,6 +151,10 @@ typedef enum {
 #define MV2_IS_BROADCOM_CARD(_x) \
     ((_x) > MV2_HCA_BROADCOM_START && (_x) < MV2_HCA_BROADCOM_END)
 
+/* Check if given card is Yunsilicon card or not */
+#define MV2_IS_YUNSILICON_CARD(_x) \
+    ((_x) > MV2_HCA_YUNSILICON_START && (_x) < MV2_HCA_YUNSILICON_END)
+
 /* Architecture Type 
  * Layout:
  *    1 - 1000 - Intel architectures
diff --git a/src/mpid/ch3/channels/common/src/detect/hca/mv2_hca_detect.c b/src/mpid/ch3/channels/common/src/detect/hca/mv2_hca_detect.c
index 280cede..42fa648 100644
--- a/src/mpid/ch3/channels/common/src/detect/hca/mv2_hca_detect.c
+++ b/src/mpid/ch3/channels/common/src/detect/hca/mv2_hca_detect.c
@@ -68,6 +68,7 @@ static mv2_multirail_info_type g_mv2_multirail_info = mv2_num_rail_unknown;
 #define MV2_STR_NES0         "nes0"
 #define MV2_STR_QEDR         "qedr"
 #define MV2_STR_BRDCM        "bnxt"
+#define MV2_STR_XSC          "xscale"
 
 #if ENABLE_PVAR_MV2 && CHANNEL_MRAIL
 MPI_T_cvar_handle mv2_force_hca_type_handle = NULL;
@@ -132,6 +133,9 @@ static mv2_hca_types_log_t mv2_hca_types_log[] =
     /* Broadcom RoCE Cards */
     {MV2_HCA_BROADCOM_BNXTRE,"MV2_HCA_BROADCOM_BNXTRE"},
 
+    /* Yunsilicon RoCE Cards */
+    {MV2_HCA_YUNSILICON_XSCALE,"MV2_HCA_YUNSILICON_XSCALE"},
+
     /* Last Entry */
     {MV2_HCA_LAST_ENTRY,    "MV2_HCA_LAST_ENTRY"},
 };
@@ -143,6 +147,7 @@ static mv2_network_types_log_t mv2_network_types_log[] =
     {MV2_NETWORK_CLASS_IWARP,   "MV2_NETWORK_CLASS_IWARP"},
     {MV2_NETWORK_CLASS_MARVEL,  "MV2_NETWORK_CLASS_MARVEL"},
     {MV2_NETWORK_CLASS_BROADCOM,"MV2_NETWORK_CLASS_BROADCOM"},
+    {MV2_NETWORK_CLASS_YUNSILICON,"MV2_NETWORK_CLASS_YUNSILICON"},
 };
 
 
@@ -417,6 +422,9 @@ mv2_hca_type mv2_new_get_hca_type(struct ibv_context *ctx,
     } else if (!strncmp(dev_name, MV2_STR_BRDCM, 4)) {
         hca_type = MV2_HCA_BROADCOM_BNXTRE;
 
+    } else if (!strncmp(dev_name, MV2_STR_XSC, 6)) {
+        hca_type = MV2_HCA_YUNSILICON_XSCALE;
+
     } else {
         hca_type = MV2_HCA_UNKWN;
     }    
@@ -651,6 +659,9 @@ mv2_hca_type mv2_get_hca_type( struct ibv_device *dev )
     } else if (!strncmp(dev_name, MV2_STR_BRDCM, 4)) {
         hca_type = MV2_HCA_BROADCOM_BNXTRE;
 
+    } else if (!strncmp(dev_name, MV2_STR_XSC, 6)) {
+        hca_type = MV2_HCA_YUNSILICON_XSCALE;
+
     } else {
         hca_type = MV2_HCA_UNKWN;
     }    
diff --git a/src/mpid/ch3/channels/mrail/src/gen2/ibv_param.c b/src/mpid/ch3/channels/mrail/src/gen2/ibv_param.c
index 6e8c33f..7b13588 100644
--- a/src/mpid/ch3/channels/mrail/src/gen2/ibv_param.c
+++ b/src/mpid/ch3/channels/mrail/src/gen2/ibv_param.c
@@ -3082,6 +3082,28 @@ static void rdma_set_default_parameters_numrail_4(struct
 		rdma_get_fallback_threshold = 0;	
 	}
 
+	else if (MV2_IS_ARCH_HCA_TYPE
+	         (proc->arch_hca_type, MV2_ARCH_INTEL_GENERIC,
+			 MV2_HCA_YUNSILICON_XSCALE)) {
+		rdma_vbuf_total_size = 10 * 1024 + EAGER_THRESHOLD_ADJUST;
+		rdma_fp_buffer_size = 5 * 1024;
+		rdma_iba_eager_threshold = VBUF_BUFFER_SIZE;
+		rdma_eagersize_1sc = 8 * 1024;
+		rdma_put_fallback_threshold = 8 * 1024;
+		rdma_get_fallback_threshold = 0;
+	}
+
+	else if (MV2_IS_ARCH_HCA_TYPE
+	         (proc->arch_hca_type, MV2_ARCH_ANY,
+			 MV2_HCA_YUNSILICON_XSCALE)) {
+		rdma_vbuf_total_size = 10 * 1024 + EAGER_THRESHOLD_ADJUST;
+		rdma_fp_buffer_size = 5 * 1024;
+		rdma_iba_eager_threshold = VBUF_BUFFER_SIZE;
+		rdma_eagersize_1sc = 8 * 1024;
+		rdma_put_fallback_threshold = 8 * 1024;
+		rdma_get_fallback_threshold = 0;
+	}
+
     else if (MV2_IS_ARCH_HCA_TYPE
              (proc->arch_hca_type, MV2_ARCH_AMD_MAGNY_COURS_24,
               MV2_HCA_MLX_CX_QDR)) {
@@ -3907,6 +3929,28 @@ static void rdma_set_default_parameters_numrail_3(struct
 		rdma_get_fallback_threshold = 0;	
 	}
 
+	else if (MV2_IS_ARCH_HCA_TYPE
+	         (proc->arch_hca_type, MV2_ARCH_INTEL_GENERIC,
+			 MV2_HCA_YUNSILICON_XSCALE)) {
+		rdma_vbuf_total_size = 10 * 1024 + EAGER_THRESHOLD_ADJUST;
+		rdma_fp_buffer_size = 5 * 1024;
+		rdma_iba_eager_threshold = VBUF_BUFFER_SIZE;
+		rdma_eagersize_1sc = 8 * 1024;
+		rdma_put_fallback_threshold = 8 * 1024;
+		rdma_get_fallback_threshold = 0;
+	}
+
+	else if (MV2_IS_ARCH_HCA_TYPE
+	         (proc->arch_hca_type, MV2_ARCH_ANY,
+			 MV2_HCA_YUNSILICON_XSCALE)) {
+		rdma_vbuf_total_size = 10 * 1024 + EAGER_THRESHOLD_ADJUST;
+		rdma_fp_buffer_size = 5 * 1024;
+		rdma_iba_eager_threshold = VBUF_BUFFER_SIZE;
+		rdma_eagersize_1sc = 8 * 1024;
+		rdma_put_fallback_threshold = 8 * 1024;
+		rdma_get_fallback_threshold = 0;
+	}
+
     else if (MV2_IS_ARCH_HCA_TYPE
              (proc->arch_hca_type, MV2_ARCH_AMD_MAGNY_COURS_24,
               MV2_HCA_MLX_CX_QDR)) {
@@ -4731,6 +4775,28 @@ static void rdma_set_default_parameters_numrail_2(struct
 		rdma_get_fallback_threshold = 0;	
 	}
 
+	else if (MV2_IS_ARCH_HCA_TYPE
+	         (proc->arch_hca_type, MV2_ARCH_INTEL_GENERIC,
+			 MV2_HCA_YUNSILICON_XSCALE)) {
+		rdma_vbuf_total_size = 10 * 1024 + EAGER_THRESHOLD_ADJUST;
+		rdma_fp_buffer_size = 5 * 1024;
+		rdma_iba_eager_threshold = VBUF_BUFFER_SIZE;
+		rdma_eagersize_1sc = 8 * 1024;
+		rdma_put_fallback_threshold = 8 * 1024;
+		rdma_get_fallback_threshold = 0;
+	}
+
+	else if (MV2_IS_ARCH_HCA_TYPE
+	         (proc->arch_hca_type, MV2_ARCH_ANY,
+			 MV2_HCA_YUNSILICON_XSCALE)) {
+		rdma_vbuf_total_size = 10 * 1024 + EAGER_THRESHOLD_ADJUST;
+		rdma_fp_buffer_size = 5 * 1024;
+		rdma_iba_eager_threshold = VBUF_BUFFER_SIZE;
+		rdma_eagersize_1sc = 8 * 1024;
+		rdma_put_fallback_threshold = 8 * 1024;
+		rdma_get_fallback_threshold = 0;
+	}
+
     else if (MV2_IS_ARCH_HCA_TYPE
              (proc->arch_hca_type, MV2_ARCH_AMD_MAGNY_COURS_24,
               MV2_HCA_MLX_CX_QDR)) {
@@ -5555,6 +5621,28 @@ static void rdma_set_default_parameters_numrail_1(struct
 		rdma_get_fallback_threshold = 0;	
 	}
 
+	else if (MV2_IS_ARCH_HCA_TYPE
+	         (proc->arch_hca_type, MV2_ARCH_INTEL_GENERIC,
+			 MV2_HCA_YUNSILICON_XSCALE)) {
+		rdma_vbuf_total_size = 10 * 1024 + EAGER_THRESHOLD_ADJUST;
+		rdma_fp_buffer_size = 5 * 1024;
+		rdma_iba_eager_threshold = VBUF_BUFFER_SIZE;
+		rdma_eagersize_1sc = 8 * 1024;
+		rdma_put_fallback_threshold = 8 * 1024;
+		rdma_get_fallback_threshold = 0;
+	}
+
+	else if (MV2_IS_ARCH_HCA_TYPE
+	         (proc->arch_hca_type, MV2_ARCH_ANY,
+			 MV2_HCA_YUNSILICON_XSCALE)) {
+		rdma_vbuf_total_size = 10 * 1024 + EAGER_THRESHOLD_ADJUST;
+		rdma_fp_buffer_size = 5 * 1024;
+		rdma_iba_eager_threshold = VBUF_BUFFER_SIZE;
+		rdma_eagersize_1sc = 8 * 1024;
+		rdma_put_fallback_threshold = 8 * 1024;
+		rdma_get_fallback_threshold = 0;
+	}
+
     else if (MV2_IS_ARCH_HCA_TYPE
              (proc->arch_hca_type, MV2_ARCH_AMD_MAGNY_COURS_24,
               MV2_HCA_MLX_CX_QDR)) {
@@ -6356,6 +6444,28 @@ static void rdma_set_default_parameters_numrail_unknwn(struct
 		rdma_get_fallback_threshold = 0;	
 	}
 
+	else if (MV2_IS_ARCH_HCA_TYPE
+	         (proc->arch_hca_type, MV2_ARCH_INTEL_GENERIC,
+			 MV2_HCA_YUNSILICON_XSCALE)) {
+		rdma_vbuf_total_size = 10 * 1024 + EAGER_THRESHOLD_ADJUST;
+		rdma_fp_buffer_size = 5 * 1024;
+		rdma_iba_eager_threshold = VBUF_BUFFER_SIZE;
+		rdma_eagersize_1sc = 8 * 1024;
+		rdma_put_fallback_threshold = 8 * 1024;
+		rdma_get_fallback_threshold = 0;
+	}
+
+	else if (MV2_IS_ARCH_HCA_TYPE
+	         (proc->arch_hca_type, MV2_ARCH_ANY,
+			 MV2_HCA_YUNSILICON_XSCALE)) {
+		rdma_vbuf_total_size = 10 * 1024 + EAGER_THRESHOLD_ADJUST;
+		rdma_fp_buffer_size = 5 * 1024;
+		rdma_iba_eager_threshold = VBUF_BUFFER_SIZE;
+		rdma_eagersize_1sc = 8 * 1024;
+		rdma_put_fallback_threshold = 8 * 1024;
+		rdma_get_fallback_threshold = 0;
+	}
+
     else if (MV2_IS_ARCH_HCA_TYPE
              (proc->arch_hca_type, MV2_ARCH_INTEL_HARPERTOWN_8,
               MV2_HCA_MLX_CX_QDR)) {
@@ -6538,6 +6648,8 @@ void rdma_set_default_parameters(struct mv2_MPIDI_CH3I_RDMA_Process_t *proc)
         rdma_max_inline_size = 64;
     } else if (MV2_HCA_BROADCOM_BNXTRE == proc->hca_type) {
         rdma_max_inline_size = 96;
+    } else if (MV2_HCA_YUNSILICON_XSCALE == proc->hca_type) {
+        rdma_max_inline_size = 64;
     } else {
         rdma_max_inline_size = 128 + INLINE_THRESHOLD_ADJUST;
     }