Fwd: [mvapich-discuss] CPU Binding Policy

[Hao Wang]

Hey Vaibhav Dutt

For your node, if you use the scatter policy with odd process number, 
such as

mpirun_rsh -np 5 -hostfile youhostfile MV2_CPU_BINDING_POLICY=scatter 
yourapplications

Machine (16GB)
   Socket L#0
     L2 L#0 (6144KB)
       L1 L#0 (32KB) + Core L#0 + PU L#0 (P#0)
       L1 L#1 (32KB) + Core L#1 + PU L#1 (P#4)
     L2 L#1 (6144KB)
       L1 L#2 (32KB) + Core L#2 + PU L#2 (P#2)
       L1 L#3 (32KB) + Core L#3 + PU L#3 (P#6)
   Socket L#1
     L2 L#2 (6144KB)
       L1 L#4 (32KB) + Core L#4 + PU L#4 (P#1)
       L1 L#5 (32KB) + Core L#5 + PU L#5 (P#5)
     L2 L#3 (6144KB)
       L1 L#6 (32KB) + Core L#6 + PU L#6 (P#3)
       L1 L#7 (32KB) + Core L#7 + PU L#7 (P#7)

rank 0 will be bound to P#0, rank 1 will be bound to P#1, rank 2 will be 
bound to P#2, rank 3 will be bound to P#3, and rank 4 will be bound to P#4.

You can get detailed information about the behavior from the user guide 
section 6.4.1:

http://mvapich.cse.ohio-state.edu/support/user_guide_mvapich2-1.7_alpha2.html#x1-450006.4.1

Thanks

- Hao



On 6/9/2011 3:29 PM, Dhabaleswar K. Panda wrote:
> Hao - can you take a look at it and answer.
>
> DK
>
> ---------- Forwarded message ----------
> From: vaibhav dutt
> Date: Thursday, June 9, 2011
> Subject: [mvapich-discuss] CPU Binding Policy
> To: mvapich-discuss at cse.ohio-state.edu
>
>
> Hi,
>
> I am trying to execute an application on an 8 node cluster, where each
> node has two Intel Xeon quad cores.
> I have one doubt regarding the CPU binding policy. Below is the output
> I got by using hwloc for my node's topology.
>
> Machine (16GB)
>    Socket L#0
>      L2 L#0 (6144KB)
>        L1 L#0 (32KB) + Core L#0 + PU L#0 (P#0)
>        L1 L#1 (32KB) + Core L#1 + PU L#1 (P#4)
>      L2 L#1 (6144KB)
>        L1 L#2 (32KB) + Core L#2 + PU L#2 (P#2)
>        L1 L#3 (32KB) + Core L#3 + PU L#3 (P#6)
>    Socket L#1
>      L2 L#2 (6144KB)
>        L1 L#4 (32KB) + Core L#4 + PU L#4 (P#1)
>        L1 L#5 (32KB) + Core L#5 + PU L#5 (P#5)
>      L2 L#3 (6144KB)
>        L1 L#6 (32KB) + Core L#6 + PU L#6 (P#3)
>        L1 L#7 (32KB) + Core L#7 + PU L#7 (P#7)
>
> If I use block rank placement and scatter CPU binding policy, then do
> the  odd ranks would be placed on on odd numbered cores and even ranks
> on
> even numbered cores?
>
>