[mvapich-discuss] Any plausible optimizations?

[Laurence Marks]

For a small cluster of Dual Quad-Core  E5410  @ 2.33GHz 1333 FSB with
8GB 667MHz DDR2 FB-DIMM the total time for mpi jobs is scaling roughly
as

Total Time ~ C1/(Total Number of mpi) *([Jobs per Bus]**F1) + C2

Where
Jobs per Bus = max(1,[mpi per Node]/2) i.e. dual bus architecture
C1 and C2 depend upon the specific benchmark (C1 >> C2)
F1 ~ 0.6

For reference, I'm using mvapich (not mpd) and infiniband; the
infiniband is fast enough

Among the slew of different possible optimization options in mvapich,
I wonder if there anything which might increase F1, i.e. what I
understand as the FSB limiting term?

-- 
Laurence Marks
Department of Materials Science and Engineering
MSE Rm 2036 Cook Hall
2220 N Campus Drive
Northwestern University
Evanston, IL 60208, USA
Tel: (847) 491-3996 Fax: (847) 491-7820
email: L-marks at northwestern dot edu
Web: www.numis.northwestern.edu
Commission on Electron Diffraction of IUCR
www.numis.northwestern.edu/IUCR_CED